1. Field of the Invention
The present invention relates to an integrated circuit having one or more buffers.
2. Description of the Prior Art
An integrated circuit (IC) typically communicates to external devices through electrical conductors driven by output buffers. Another type of buffer, referred to as a "clock driver", is used to distribute clock signals. The clock driver in some cases is located on the same integrated circuit as the circuitry that receives the clock signals. For either on-chip or off-chip drive applications, a buffer is designed to provide adequate current drive capability to charge and discharge the capacitive load presented by the driven conductors (and driven circuitry) at a sufficiently fast rate to allow signals to be sent at the desired speed. The speed at which a buffer can raise a voltage from a low logic level (typically 0 volts) to a high logic level (typically 3 or 5 volts) is referred to as the "rise time". Similarly, the speed at which the buffer can reduce the voltage from high to low levels is the "fall time". With CMOS integrated circuits, the speed of data communications to external devices presently ranges up to several tens of million bits per second, with increases to over one hundred million bits per second likely in the near future. Therefore, the rise and fall times are typically required to be less than about 10 nanoseconds at present, with significant reductions required for the future.
One problem associated with signals having rapid rise and fall times is the electrical noise they produce in other parts of the integrated circuit. That is, stray capacitance and inductance cause some of the signal energy to couple to other portions of the integrated circuit, or to other conductors external to the IC. In addition, inductance in the ground path causes voltage spikes to appear due to rapid current variations caused by the switching of large buffers. These problems generally become more severe as the rise and fall times become shorter. In most cases, integrated circuit buffers are designed so that the rise and fall times are sufficiently fast to drive the load under worst case conditions. For CMOS integrated circuits, the worst case conditions are slower than nominal process speeds, low power supply voltages, and high operating temperatures. However, under the best case conditions, the rise and fall times may then be so short as to generate excessive noise. The "process speed" refers to the fact that due to the tolerances for a given IC production process, some IC's turn out to be "fast", and others "slow", as compared to IC's produced by an average or nominal process. That is, a given production run may produce devices that switch signals more quickly than average, being referred to as a "fast" process, and vice-versa for a "slow" process. Hence, a buffer design that satisfies the speed requirements may violate the noise requirements, and vice-versa.
It is desirable to have an integrated circuit that generates low noise while having the ability to communicate at a sufficiently high data rate over conductors and other circuitry presenting a significant capacitive load. One technique for controlling buffer switching speed, and hence the noise produced, is shown in FIG. 1. The pre-driver transistors 102 and 103 supply a drive signal to pull-up output transistor 100, whereas pre-driver transistors 106 and 107 supply a drive signal to pull-down output transistor 101. A control voltage VCP increases when factors such as process speed, temperature, and power supply voltage (for example) tend to increase the switching speed. This increase of VCP reduces the gate-to-source voltage, and hence the conductivity, of the p-channel transistor 105, thereby reducing the drive signal to output transistor 101, which controls the buffer fall time. Inversely, the voltage VCP decreases, so as to increase the conductivity of transistor 105, when these factors tend to decrease the switching speed. (The control voltage VCN is generated so as to similarly affect the conductivity of the n-channel transistor 104, thereby controlling the drive to the output transistor 100, and hence the buffer rise time.) In this manner, the buffer switching speed, and hence noise, is held more constant with respect to variations in these factors. The output load driven by this buffer is shown as capacitance C.sub.load.
One method of generating the control voltages VCP and VCN is shown in U.S. Pat. No. 4,823,029, co-assigned herewith. The type of static circuits for generating the control voltages as shown in FIGS. 2 through 5 therein are successful in many applications. However, accounting for all possible variations in the factors that influence the switching speed is difficult when a static circuit is used to generate the DC control voltage. Another method of controlling an output buffer is shown in U.S. Pat. No. 4,567,378, wherein the buffer output signal is compared to the output of a ramp generator. If the output signal rises or falls faster than the ramp signal, then a feedback signal adjusts the speed of the buffer to more closely correspond to the ramp signal. However, that technique monitors the output signal at each buffer, which requires extra monitor circuitry for each buffer, and ramp circuitry for each buffer.